Simics three-day education plan

So I am about to give a three-day course on simulation basics at St. Petersburg this August. So, what can I try to teach students in 3 days, eight hours per day?

My current idea is to start from a CPU model and move eventually to platform devices, at least some of them. We might not accomplish everything planned (this depends on students’ background in CS, their programming skills and interest after all). In order to reach anything though, the target architecture has to have several properties.

  1. Being not overly complex. IA-32 is definitely no go; neither is any other CISC — they incorporate too much of ~~nonsensical~~ historical stuff. RISCs look better. So I thought about ARM (too complex as well), MIPS (easy, but boring; everyone does MIPS), Alpha (simple CPU, but what about peripheral devices?).
  2. It should have at least a working assembler, or better a compiler. It’s no good having a computer model and being unable to run any code on it. And we definitely will not have time to write a toolchain ourselves from scratch.

At first, I thought to make a “hardware” Forth implementation or a hardware Brainfuck CPU, or CHIP16. The first and second are not full-platform enough, and I have no time to devise full-system specs (interrupt controllers, timers, IO) for them. The latter was also tempting, but I decided that it is also too complex for three days; there is no fun in having a game console model not ready enough to run any games.

Therefore, I stopped on OpenRISC project. The OR1k specification is what I’ll base this course on. The architecture looks promising because of several factors.

  1. It is open, actively developed and used. Knowledge of OR1k alone might be useful some day.
  2. It is RISC, it has 32 bit baseline.
  3. It has toolchains in place. GCC and LLVM compliers support it. There are already firmware images if one is really serious about running useful code on a model.
  4. The most important thing: the spec is modular. A lot of things are optional. This allows to keep extending a Simics model until alloted time runs out, and still have something complete.

So, here’s the initial feature plan for implementing OR1k model. Going from basic ISA and registers though optional things to basic peripheral devices.

  1. GPRs and basic SPRs
  2. ORBIS32 instruction set
  3. Exceptions support
  4. Implementation of TLB and idea of MMU
  5. Tick timer facility (peripheral device)
  6. PIC (peripheral device)
  7. Data cache model
  8. ORFPX32 (floating point ISA)

In fact, if we get to the tick timer, I will consider the project to be a success.

Written by Grigory Rechistov in Uncategorized on 09.05.2014. Tags: openrisc, or1k, simics,

Copyright © 2018 Grigory Rechistov